(a) Field of the Invention
The present invention relates to an LCD, a panel and a method for compensating for gate signal delay. More specifically, the present invention relates to an apparatus and a method for providing a gate signal delay compensating LCD, a panel and a method to be easily implemented without an additional driving integrated circuit (IC) and to compensate for gate-on signal delay due to resistance and capacitance of a gate line without unnecessarily affecting the LCD panel characteristics.
(b) Description of the Related Art
The thin film transistor liquid crystal display (TFT-LCD) is one of major LCDs, and a target project for the LCD is to increase the size of the LCD panel as well as its resolution. The bigger size and higher resolution of the LCD panel requires longer data lines and gate lines in the panel, which increases line resistance. More crossover points between the lines increase parasitic capacitance of each line. Particularly, when designing a panel of high through-hole ratio to be required in the future, the increased overlaps of the pixels and lines delay signals greatly.
FIG. 3 shows the above-described gate signal delay of a conventional LCD panel. Referring to FIG. 3, a gate signal is provided as a square wave at an input point. However, when transmitted to a corresponding line on the panel, the signal is delayed at an end of the gate line because of the line resistance and capacitance. Accordingly, the square wave is distorted. The gate signal at the end of the gate line has a delayed waveform because of the distortion. The gate signal delay worsens charging characteristics of each pixel in the LCD panel, because the longer signal delay shortens the gate-on interval of the gate signal. This causes the charging amount at each pixel to fall short from the specification.
To solve the deteriorated image problem caused by the signal delay at the large LCD panel of high resolution, a driving method for supplying signals at both ends of the gate lines on the LCD panel is suggested. However, this method increases the number of driver IC, and therefore, hindering cost competitiveness.